I am presently interested in algorithms and architectures for low power video codec circuits. These circuits are typically intended to be used as dedicated hardware accelerators in smartphones and other energy-constrained applications. Previously, I had worked on fast statistical techniques for evaluating SRAM failure due to process variation.

From 2011 to 2012, I was part of the team that designed a video decoder for H.265/HEVC, the latest video coding standard. The team included Chao-Tsung Huang and Chiraag Juvekar and was guided by Vivienne Sze and Anantha Chandrakasan. Here’s a video of our prototype demo system with our chip (“MIT HEVC Decoder” at the start of the video) decoding a 2160p video sequence which is then displayed on four full-HD (1080p) monitors. And here’s me explaining our work at the demo session of the International Solid-State Circuits Conference (ISSCC) in Feb. 2013.

Publications

M. Tikekar, C.-T. Huang, C. Juvekar, V. Sze, A. Chandrakasan, “A 249 MPixel/s HEVC Video-Decoder Chip for 4K Ultra HD Applications,” IEEE Journal of Solid State Circuits (to appear).

M. Qazi, M. Tikekar, L. Dolecek, D. Shah, A. P. Chandrakasan, “Technique for Efficient Evaluation of SRAM Timing Failure,” IEEE Transactions on Very Large Scale Integration Systems, vol.21, no.8, pp.1558,1562, Aug. 2013. IEEE

C.-T. Huang, M. Tikekar, C. Juvekar, V. Sze, A. Chandrakasan, “A 249Mpixel/s HEVC Video-Decoder Chip for Quad Full HD Applications,” IEEE International Solid State Circuits Conference (ISSCC), pp. 162-163, Feb 2013. IEEE

M. Tikekar, “Circuit Implementations for High-Efficiency Video Coding Tools”, S.M. Thesis, Massachusetts Institute of Technology, June 2012. Dspace

M. Qazi, M. Tikekar, L. Dolecek, D. Shah, A. Chandrakasan, “Loop Flattening & Spherical Sampling: Highly Efficient Model Reduction Techniques for SRAM Yield Analysis,” Design, Automation and Test in Europe (DATE), pp. 801-806, March 2010. IEEE